1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
In order to supply a test pattern to a device under test (DUT) to be tested, so as to test its operation and to judge the quality of the DUT, a test apparatus is employed. Such a test apparatus mounts: a pattern generator (PG) which generates a test pattern to be supplied to the DUT; and a timing generator (TG) which determines a timing at which the test pattern is supplied to the DUT. The period (frequency) of the test pattern is also referred to as the “test rate”. The test apparatus is required to have a function whereby the test rate is changed as desired.
Typical timing generators each include analog or digital delay circuits. With such an arrangement, the delay provided by the variable delay circuit is set according to the test rate. That is to say, such an arrangement delays the test pattern itself, thereby providing a desired test rate.
Alternatively, by means of the variable delay circuit, such an arrangement applies a desired delay to a set signal or otherwise a reset signal which determines the transition timing of the test pattern. With such an arrangement, the test pattern is switched in synchronization with the set signal or reset signal thus delayed.
In recent years, the operating speed of semiconductor devices has been steadily increasing. The increased device operating speed requires the test rate to be improved. In the near future, such a test apparatus will be required to have a function of controlling the test rate with a very high resolution on the order of sub-picoseconds. Thus, the delay circuit employed in the timing generator is required to have a precision that is maintained at high level.
Here, the delay time provided by the delay circuit is affected by the operating current, the temperature, or the power supply voltage. Thus, in order to configure such a timing generator having high precision, the power supply voltage and the temperature are preferably maintained for the overall configuration of the IC (Integrated Circuit) chip including the delay circuit.
FIG. 1 is a diagram showing a configuration of a semiconductor device 1002 according to a comparison technique.
The semiconductor device 1002 includes a circuit block 1030 including multiple flip-flops or latches (which will be referred to as the “flip-flops”) 1032. The flip-flops 1032 intermittently and repeatedly switch the state between (i) an operating state in which state transitions are generated in synchronization with a clock CLK, which requires current consumption; and (ii) a stopped state in which the state transitions are stopped, which requires substantially no operating current.
With such an arrangement, the duty ratio (time ratio) between the operating state and the stopped state depends on the pattern of the input signal SIN supplied to the circuit block 1030. Thus, the operating current IDD of the circuit block changes with the passage of time.
With such an arrangement, the change in the operating current IDD of the circuit block 1030 leads to a change in the surrounding temperature and/or a change in the power supply voltage VDD. The change in the temperature or in the power supply voltage VDD has effects on the operations of other circuit blocks included in the test apparatus, examples of which include a pattern generator which generates a pattern to be supplied to the DUT, and a timing generator configured to control the pattern transition timing. This leads to a problem of jitter being superimposed on the generated signal.
In order to solve such a problem, a technique has been proposed in which a heater circuit 1040 (which is also referred to as a “load balance circuit”) is connected in parallel with the circuit block 1030. With such a technique, the heater circuit 1040 is controlled such that the sum total of the operating current IDD of the circuit block 1030 and the consumed current (which will also be referred to as the “compensation current”) ICMP provided by the heater circuit 1040 is maintained at a constant level.
The operating current IDD of the circuit block 1030 changes according to process variation. In order to solve such a problem, the heater circuit 1040 is configured to be capable of adjusting the amount of compensation current ICMP so as to cancel out the effect of the process variation. Specifically, the heater circuit 1040 includes multiple heater cells 1042 arranged in parallel with the circuit block 1030. The heater circuit 1040 is configured to be capable of controlling the compensation current ICMP according to the number of heater cells which are turned on.
Typically, with regard to process variation, there is a correlation between the operating current IDD of the circuit block 1030 and the delay amount provided by a delay element (not shown) built into the circuit block 1030. Thus, a method is employed in which the operating current IDD of the circuit block 1030 is estimated based on the delay amount provided by the delay circuit built into the circuit block 1030. More specifically, the operating current IDD of the circuit block 1030 is estimated by estimating the oscillation period of an oscillator having a circuit loop including the delay circuit. The number of heater cells being in ON state of the heater circuit 1040 is determined based on the operating current IDD thus estimated.
With such a current compensation technique employing the heater circuit 1040, such an arrangement requires the heater circuit 1040 in addition to the circuit block 1030. This leads to a problem of an increase in the circuit scale.
In particular, if the fluctuation range of the operating current IDD of the circuit block 1030 becomes greater, there is a need to increase the range of the compensation current ICMP to be generated by the heater circuit 1040. Thus, in order to provide high-precision current compensation, there is a need for an explosive increase in the circuit scale of the heater circuit 1040, which is a problem.
In addition, in a case in which there is a small correlation between the operating current IDD and the delay amount provided by the delay element built into the circuit block 1030, this leads to an increase in the error between the estimated value of the operating current IDD and the actual value. This leads to a problem in that the sum total of the operating current IDD and the compensation current ICMP cannot be maintained at a constant level in the operation of the heater circuit 1040.
The aforementioned problems are not restricted to such a timing generator. Rather, such problems can occur in various kinds of semiconductor devices.